By explicitly assigning a data type, you can force fixed-point data types on output ports of the HDL Cosimulation block. You can also assign an explicit data type, with optional Fraction Length. As an example, if the HDL simulator returns the VHDL data type STD_LOGIC_VECTOR for a signal of size N bits, the data type ufixN is forced on the output port. If Simulink cannot determine the data type of the signal connected to the output port, it queries the HDL simulator for the data type of the port. For example, if you connect a Signal Specification block to an output, Inherit forces the data type specified by the Signal Specification block onto the output port. If they do not match, Simulink generates an error message. The block checks that the inherited word length matches the word length queried from the HDL simulator. Select Inherit to automatically determine the data type.
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January 2023
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